Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 97)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

5 HNPREQ

HNP Request Bit

Set to initiate the HNP when the controller is in the Device mode (B).

Set to accept the HNP when the controller is in the Host mode (A).

Cleared by hardware after the HNP completion.

4 SRPREQ

SRP Request Bit

Set to initiate the SRP when the controller is in Device mode.

Cleared by hardware when the controller is initiating a SRP.

3 SRPSEL

SRP Selection Bit

Set to choose VBUS pulsing as SRP method.

Clear to choose data line pulsing as SRP method.

2 VBUSHWC

VBus Hardware Control Bit

Set to disable the hardware control over the UVCON pin.

Clear to enable the hardware control over the UVCON pin.

1 VBUSREQ

VBUS Request Bit

Set to assert the UVCON pin in order to enable the VBUS power supply

generation. This bit shall be used when the controller is in the Host mode.

Cleared by hardware when VBUSRQC is set.

0 VBUSRQC

VBUS Request Clear Bit

Set to deassert the UVCON pin in order to enable the VBUS power supply

generation. This bit shall be used when the controller is in the Host mode.

Cleared by hardware immediately after the set.

Table 108. OTGTCON Register

OTGTCON (1.E6h) – USB OTG Timer Control Register

7 6 5 4 3 2 1 0

1 PAGE1:0 - - VALUE2:0

Bit

Number

Bit

Mnemonic

Description

7 1

OTGTCON Pagination

This bit must be set to access the OTGTCON register.

6-5 PAGE1:0

Timer Page Access Bit

Set/clear to access a special timer register.

See Section “OTG Timers Customizing” for more details.

4-3 -

Reserved

The value read from these bits is always 0. Do not set these bits.

2-0 VALUE2:0

Value Bit

Set to initialize the new value of the timer.

See Section “OTG Timers Customizing” for more details.

Bit

Number

Bit

Mnemonic Description

1 2 ... 92 93 94 95 96 97 98 99 100 101 102 ... 262 263

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