Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 221)

221

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0X10 0010b

Reset Value = 0000 0000b

1 TI

Transmission Interrupt Flag

Set by hardware when the Tx FIFO is not full: a character can be loaded through

SBUF.

Cleared by hardware when the Tx FIFO becomes full: no more character can be

loaded.

0 RI

Reception Interrupt Flag

Set by hardware when the Rx FIFO is not empty: character ready to be read

through SBUF.

Cleared by hardware when the Rx FIFO becomes empty: no more character to

be read.

Table 245. SIEN Register

SIEN (1.A9h) – SIO Interrupt Enable Register

7 6 5 4 3 2 1 0

- - EOTIE OEIE PEIE FEIE TIE RIE

Bit

Number

Bit

Mnemonic

Description

7-6 -

Reserved

The value read from these bits is always 0. Do not set these bits.

5 EOTIE

End Of Transmission Interrupt Enable Bit

Set to enable end of transmission interrupt generation.

Clear to disable end of transmission interrupt generation.

4 OEIE

Overrun Error Interrupt Enable Bit

Set to enable overrun error interrupt generation.

Clear to disable overrun error interrupt generation.

3 PEIE

Parity Error Interrupt Enable Bit

Set to enable parity error interrupt generation.

Clear to disable parity error interrupt generation.

2 FEIE

Framing Error Interrupt Enable Bit

Set to enable framing error interrupt generation.

Clear to disable framing error interrupt generation.

1 TIE

Transmission Interrupt Enable Bit

Set to enable transmission interrupt generation.

Clear to disable transmission interrupt generation.

0 RIE

Reception Interrupt Enable Bit

Set to enable reception interrupt generation.

Clear to disable reception interrupt generation.

Bit

Number

Bit

Mnemonic Description

1 2 ... 216 217 218 219 220 221 222 223 224 225 226 ... 262 263

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