Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 175)

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AT85C51SND3Bx

7632A–MP3–03/06

Assembly code: mov #, direct

• A read of NFDAT returns to the CPU the byte contained in that register, but does not

launch an extra background “read cycle”.

Assembly code: mov #, direct

In all the previous examples, the NFCE line is asserted low and de-asserted at the end

of the cycle. This allows minimizing the power consumption.

Access Example Figure 80 shows a read access in a 512B page. Note that the NFCE must be held low

during the access time for that kind of memory:

Read data, TRS cleared

CPU: 40 ns setup, timing [1.5; 0.5]

[15;30] ns hold

NFCEx

NFCLE

NFALE

NFWE

NFRE

NFD[7:0]

NFCLK / 2

Read data, TRS set

CPU: 40 ns setup Timing [1; 1]

[15;30] ns hold

NFCEx

NFCLE

NFALE

NFWE

NFRE

NFD[7:0]

1 2 ... 170 171 172 173 174 175 176 177 178 179 180 ... 262 263

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