Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 211)

211

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 0000 0000b

Table 231. PSICON Register

PSICON (1.ADh) – PSI Control Register

7 6 5 4 3 2 1 0

PSEN PSBSYE PSRUNE PSWS2 PSWS1 PSWS0 - -

Bit

Number

Bit

Mnemonic

Description

7 PSEN

Interface Enable Bit

Set to enable the PSI controller.

Clear to disable the PSI controller.

6 PSBSYE

Busy Interrupt Enable Bit

Set to enable the busy interrupt.

Clear to disable the busy interrupt.

5 PSRUNE

Overrun/Underrun Interrupt Enable Bit

Set to enable the overrun interrupt.

Clear to disable the overrun interrupt.

4-2 PSWS2:0

Write Sampling Bits

Data write sampling wait states after WR signal assertion from 1 clock up to 7

clock periods

1-0 -

Reserved

The value read from these bits is always 0. Do not set these bits.

Table 232. PSISTA Register

PSISTA (1.AEh) – PSI Status Register

7 6 5 4 3 2 1 0

PSEMPTY PSBSY PSOVR PSRDY - - - -

Bit

Number

Bit

Mnemonic

Description

7 PSEMPTY

FIFO Empty Flag

Set by hardware when the FIFO is empty.

Cleared by hardware when at least one data byte is present in the FIFO.

6 PSBSY

Busy Flag

Set by hardware when the FIFO becomes not empty (host has sent data with

SA0

= H).

Can be set or cleared by software.

5 PSRUN

Overrun/Underrun Flag

Overrun

Set by hardware when the host sends a data and the FIFO is full.

Clear by software to acknowledge the overrun condition.

Underrun

Set by hardware when the host reads a data and the FIFO is empty.

Clear by software to acknowledge the underrun condition.

4 PSRDY

Ready Flag

Set by hardware when a data is ready to be sent to the host.

Cleared by hardware at the end of a host read cycle.

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