Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 72)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 82. TMOD Register

TMOD (0.89h) – Timer/Counter Mode Control Register

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit

Number

Bit

Mnemonic Description

7GATE1

Timer 1 Gating Control Bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to enable Timer 1 only while INT1

pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer Select Bit

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

5M11

Timer 1 Mode Select Bits

Refer to Table 80 for Timer 1 operation.4M01

3GATE0

Timer 0 Gating Control Bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while

INT0 pin is high and TR0 bit is set.

2C/T0#

Timer 0 Counter/Timer Select Bit

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

1M10

Timer 0 Mode Select Bit

Refer to Table 78 for Timer 0 operation.0M00

Table 83. TH0 Register

TH0 (0.8Ch) – Timer 0 High Byte Register

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number

Bit

Mnemonic

Description

7-0 High Byte of Timer 0

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 262 263

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