Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 26)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = XX00 0XXXb

(1)

Note: 1. Reset value depends on the power supply presence and on the internal reset source.

Reset Value = 0000 0000b

6 HVDET

High Voltage Detect Flag

Set by hardware when 3V is detected on HVDD pin.

Cleared by hardware when 3V is not detected on HVDD pin.

5-3 -

Reserved

The value of these bits is always 0. Do not set these bits.

2 WDTRST

Watchdog Timer Reset Flag

Set by hardware when the watchdog timer has overflowed triggering and internal

reset.

Must be cleared by software at power-up.

1 EXTRST

External Reset Flag

Set by hardware when the external RST pin is asserted (warm reset).

Must be cleared by software at power-up.

0 PFDRST

Power Failure Detector Reset Flag

Set by hardware when the power voltage has been triggered outside its specified

value (cold reset).

Must be cleared by software at power-up.

Table 22. VBAT Register

VBAT (0.85h) – Battery Voltage Monitor Register

7 6 5 4 3 2 1 0

VBEN VBERR - VB4 VB3 VB2 VB1 VB0

Bit

Number

Bit

Mnemonic

Description

7 VBEN

Battery Monitor Enable Bit

Set to enable the battery monitoring.

Cleared by hardware at the end of conversion

6 VBERR

Battery Monitor Error Flag

Set by hardware when conversion is out of min/max values.

5 -

Reserved

The value read from this bit is always 0. Do not set this bit.

4-0 VB4:0

Battery Value

Refer to Table 18 for voltage value correspondence.

Bit

Number

Bit

Mnemonic Description

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 262 263

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