Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 219)

219

AT85C51SND3Bx

7632A–MP3–03/06

Figure 113. SIO Controller Interrupt System

Registers

Reset Value = 0000 0000b

PEIE

SIEN.3

TIE

SIEN.1

SIO

Interrupt

SINT.0

FEIE

SIEN.2

IEN0.4

RIE

SIEN.0

PEI

SINT.3

OEIE

SIEN.4

SINT.1

OEI

SINT.4

FEI

SINT.2

Request

EOTIE

SIEN.5

EOTI

SINT.5

Table 242. SCON Register

SCON (0.91h) – SIO Control Register

7 6 5 4 3 2 1 0

SIOEN PMOD1 PMOD0 PBEN STOP DLEN GBIT1 GBIT0

Bit

Number

Bit

Mnemonic

Description

7 SIOEN

SIO Enable Bit

Set to enable the Serial Input/Output port.

Clear to disable the Serial Input/Output port.

6-5 PMOD1:0

Parity Mode Bits

Refer to Table 237 for information on parity mode

4 PBEN

Parity Bit Enable Bit

Set to enable parity generation according to PMOD1:0 bits.

Clear to disable parity generation.

3 STOP

Stop Bit Number

Set to enable generation of 2 stop bits.

Clear to enable generation of 1 stop bit.

2 DLEN

Data Length Bit

Set to enable generation of 7 data bits.

Clear to enable generation of 8 data bits.

1-0 GBIT1:0

Guard Bit Number

Number of guard bits (from 0 to 3) transmitted after the last stop bit in

transmission mode.

1 2 ... 214 215 216 217 218 219 220 221 222 223 224 ... 262 263

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