Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 84)

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 97. DFD0 Register

DFD0 (1.8Ah) – DFC Channel 0 Data Flow Descriptor Register

7 6 5 4 3 2 1 0

DFD0D7 DFD0D6 DFD0D5 DFD0D4 DFD0D3 DFD0D2 DFD0D1 DFD0D0

Bit

Number

Bit

Mnemonic

Description

7-0 DFD0D7:0

Channel 0 Data Flow Descriptor Data

Write data flow descriptor to this register as detailed in Table 91.

Read to get the remaining number of data packet after a delayed abort. MSB is

read first.

Table 98. DFD1 Register

DFD1 (1.8Bh) – DFC Channel 1 Data Flow Descriptor Register

7 6 5 4 3 2 1 0

DFD1D7 DFD1D6 DFD1D5 DFD1D4 DFD1D3 DFD1D2 DFD1D1 DFD1D0

Bit

Number

Bit

Mnemonic

Description

7-0 DFD1D7:0

Channel 1 Data Flow Descriptor Data

Write data flow descriptor to this register as detailed in Table 91.

Read to get the remaining number of data packet after a delayed abort. MSB is

read first.

Table 99. DFCRC Register

DFCRC (1.8Ch) – DFC CRC Data Register

7 6 5 4 3 2 1 0

CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0

Bit

Number

Bit

Mnemonic

Description

7-0 CRCD7:0

CRC 2-byte Data FIFO

First reading of DFCRC returns the MSB of the CRC16 data while second

reading returns the LSB.

First writing to DFCRC writes the MSB of the initial value of the CRC16 data

while second writing writes the LSB.

1 2 ... 79 80 81 82 83 84 85 86 87 88 89 ... 262 263

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