Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 31)

AT85C51SND3Bx

7632A–MP3–03/06

Figure 21. DFC/NFC Clock Generator Block Diagram and Symbol

Table 27. DFC/NFC Clock Selection

MMC Clock Generator The MMC clock generator block diagram is shown in Figure 22 and is based on a fre-

quency selector followed by a frequency divider.

Frequency selection is done using MMCCKS2:0 bits in MMCCLK (see Table 35)

according to Table 28

(1)

Frequency division is done using MMCDIV4:0 bits in MMCCLK according to Table 29.

Frequency configuration (selection and division) must be done prior to enable the MMC

clock generation by setting MMCKEN bit in CKEN.

Note: 1. To allow low frequency as low as 400 KHz (frequency needed in MMC identification

phase), F

OSC

selection can be divided by 2.

Figure 22. MMC Clock Generator Block Diagram and Symbol

DNFCKS2:0 Clock Selection (F

)

000 F

OSC

(default)

001 60 MHz

010 48 MHz

011 40 MHz

100 30 MHz

101 24 MHz

110 20 MHz

111 16 MHz

DNFCKS2:0

CKSEL.7:5

CLOCK

GEN

000

001

010

011

100

101

110

111

60 MHz

48 MHz

40 MHz

30 MHz

24 MHz

20 MHz

16 MHz

DNFC

CLOCK

DFC/NFC Clock Symbol

DNFCKEN

CKEN.0

DFC Clock

OSC

NFC Clock

MMCKEN

CKEN.3

MMCCKS2:0

MMCCLK.7:5

000

001

010

011

100

101

110

111

60 MHz

48 MHz

30 MHz

24 MHz

20 MHz

16 MHz

MMC

CLOCK

MMC Clock Symbol

Clock

Divider

MMCDIV4:0

MMCCLK.4:0

MMC Clock

CLOCK

GEN

OSC

÷ 2

OSC

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 262 263

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