Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 227)

227

AT85C51SND3Bx

7632A–MP3–03/06

Data Transfer The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle

state

(1)

while the Clock Phase bit (CPHA in SPCON) defines the edges on which the

input data are sampled and the edges on which the output data are shifted (see

Figure 119 and Figure 120).

For simplicity, Figure 119 and Figure 120 depict the SPI waveforms in idealized form

and do not provide precise timing information. For timing parameters refer to the

Section “AC Characteristics”, page 246.

Note: 1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.

Figure 119. Data Transmission Format (CPHA = 0, UARTM = 0)

Figure 120. Data Transmission Format (CPHA = 1, UARTM = 0)

SS Management Figure 119 shows a SPI transmission with CPHA = 0, where the first SCK edge is the

MSB capture point. Therefore the slave starts to output its MSB as soon as it is

selected:

SS asserted to low level. SS must then be de-asserted between each byte

transmission (see

Figure 121). SPDAT must be loaded with a data before SS is

asserted again.

Note: In master mode, SPI transmission with CPHA = 0 is not allowed in case of DFC transfer.

1 2 3 4 5 6 7 8

MSB

bit 1 LSBbit 2bit 4 bit 3bit 6 bit 5

bit 1bit 2bit 4 bit 3bit 6 bit 5MSB LSB

MOSI (From Master)

MISO (From Slave)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

(to slave)

Capture point

1 2 3 4 5 6 7 8

MSB bit 1 LSBbit 2bit 4 bit 3bit 6 bit 5

bit 1bit 2bit 4 bit 3bit 6 bit 5MSB LSB

MOSI (from master)

MISO (from slave)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

(to slave)

Capture point

1 2 ... 222 223 224 225 226 227 228 229 230 231 232 ... 262 263

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