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AT85C51SND3Bx

7632A–MP3–03/06

USB Controller The AT85C51SND3Bx Implements a USB controller allowing the AT85C51SND3Bx to

act as a USB device or a USB host.

The main features of the USB controller:

• Full-speed and high-speed device.

• Full-speed host with OTG compliance.

• Automatic Data Flow Controller (DFC) transfer without CPU support.

• 2368 bytes of DPRAM.

• Up to 7 endpoints/pipes

– 1 endpoint of 64 bytes (default control),

– 2 endpoints of 512 bytes max, (one or two banks),

– 4 endpoints of 64 bytes max, (one or two banks).

Description The C51 core interfaces with the USB Controller using a set of special function registers

detailed in

Table 49, page 39.

As shown in Figure 49, the USB controller is based on seven functional blocks:

• the PLL clock (see Section “Clock Generator”, page 28) which delivers 480 MHz

clock for USB high-speed mode support.

• the USB HS/FS pad supporting speed negotiation, attach/detach and data transfer

• the USB OTG pad supporting OTG negotiation

• the device controller allowing AT85C51SND3B to act as a device

• the host controller allowing AT85C51SND3B to act as a device

• the 2368-byte dual port RAM for endpoints and pipes memory

• the interrupt controller

Figure 49. USB Controller Block Diagram

USB Connection Figure 50 shows the connection of the AT85C51SND3B to the USB connector and the

the connection of the RC filter to the UBIAS pin. DPF and DMF pins are connected

through 2 termination resistors.

Value of all discrete components is detailed in the Section “DC Characteristics”,

page 241.

UVCC

UID

DPF

DMF

DPH

UBIAS

DMH

PLL

CLOCK

Full Speed

High Speed

Device Controller

Host Controller

OTG

USB Pad

USB

Interrupt

Request

2368 Bytes

DPRAM

Interrupt

Controller

UVCON

DFC

Bus

CPU

Bus

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 262 263

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