Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 236)

236

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value= 0000 0000b

Table 255. LCDCON0 Register

LCDCON0 (1.96h) – LCD Control Register 0

7 6 5 4 3 2 1 0

BUINV LCIFS ADSUH1 ADSUH0 ACCW3 ACCW2 ACCW1 ACCW0

Bit

Number

Bit

Mnemonic

Description

7 BUINV

Busy Invert Active

Set to check busy bits selected in LCDBUM as active low.

Clear to check busy bits selected in LCDBUM as active high.

6 LCIFS

Interface Select Bit

Set to select 6800 interface type.

Clear to select 8080 interface type.

5-4 ADSUH1:0

Address Setup/Hold

Address Setup and hold length in clock periods (from 1 to 4 clock periods).

3-0 ACCW3:0

Access Cycle Width

Access width in clock periods (from 1 to 16 clock periods).

In 8080 mode, corresponds to WR or RD low state.

In 6800 mode, corresponds to E high state.

Table 256. LCDCON1 Register

LCDCON1 (1.8Eh) – LCD Control Register 1

7 6 5 4 3 2 1 0

SLW1 SLW0 RSCMD LCYCW LCYCT LCEN LCRD LCRS

Bit

Number

Bit

Mnemonic

Description

7-6 SLW1:0

Sleep Wait States

Busy check process enabled

Number of wait states between a read or write access and a busy check process

(from 1 to 4 clock periods).

Busy check process disabled

Number of wait states between two read or write accesses (from 1 to 4 clock

periods).

5 RSCMD

RS Command/Status

Set to output high level on LA0/LRS pin during busy check process.

Clear to output low level on LA0/LRS pin during busy check process.

This value depends on the LCD controller.

4 LCYCW

Deassertion Cycle Width

Set to program E or RD/WR signals deassertion time to the number of clock set

in ACCW3:0 bits.

Clear to let E or RD/WR signals deassertion time to the number of clock set in

ADSUH1:0 + SLW1:0.

1 2 ... 231 232 233 234 235 236 237 238 239 240 241 ... 262 263

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