Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 173)

173

AT85C51SND3Bx

7632A–MP3–03/06

Note that it is not possible to reset A9:8 after each command (write in NFCMD): the

device status read command is used after opening a page (for read) to poll the busy

status.

Command Sending Writing a command in NFCMD generates the following cycles:

Assembly code: mov direct, #

A write in that register re-initializes the ECC engine and the ECC FIFO. A read in that

Address Sending Writing an address in NFADC (column address) or NFADR (row address) generates the

following cycles:

Assembly code: mov direct, #

The NFADC register is used to select the column address. The NFC uses that informa-

tion to build an internal byte counter in the page, thus allowing it to stop at the end of the

page. 512B NF memories (NDB= 1) have 1 column cycle. Other NF memories have 2

column cycles.

The NFADR register is used to select the raw address, i.e. the page address. The NFC

uses that information to verify if the block is protected or not.

Both kind of information are reset after a read of a write of the NFCMD register. A read

in NFADC or NFADR returns an unexpected value.

NFCEx

NFCLE

NFALE

NFWE

NFRE

NFD[7:0]

Command

NFCLK / 2

Address