Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 9)

AT85C51SND3Bx

7632A–MP3–03/06

Clock Controller Table 4. Clock Signal Description

Memory Controllers Table 5. Secure Digital Card / MutiMediaCard Controller Signal Description

Table 6. Nand Flash / SmartMedia Card Controller Signal Description

Signal

Name

Type Description

Alternate

Function

X1 I

Input of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to

this pin. If an external oscillator is used, its output is connected to this

pin. X1 is the clock source for internal timing.

X2 O

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to

this pin. If an external oscillator is used, leave X2 unconnected.

UPVDD PWR

USB PLL Supply voltage

Connect this pin to LVDD pin.

UPVSS GND

USB PLL Circuit Ground

Connect this pin to LVSS pin.

APVDD PWR

Audio PLL Supply voltage

Connect this pin to LVDD pin.

APVSS GND

Audio PLL Circuit Ground

Connect this pin to LVSS pin.

Signal

Name

Type Description

Alternate

Function

SDCLK O

SD/MMC Clock

Data or command clock transfer.

P2.3

SDCMD I/O

SD/MMC Command Line

Bidirectional command line used for commands and responses transfer.

P2.2

SDDAT3:0 I/O

SD/MMC Data Lines

Bidirectional data lines. In 1-bit mode configuration SDDAT0 is the DAT

signal and SDDAT3:1 are not used and can be reused as I/O ports.

P2.7:4

SDINS I

SD/MMC Card Insertion Signal

SDINS is the card presence signal. A low level on this input indicates

the card is present in its slot.

Note: This signal is generated by the SD/MMC card connector.

P2.0

SDLCK I

SD Card Write Lock Signal

SDLCK is the SD Card write protected input. A low level on this pin

indicates the card is write protected.

Note: This signal is generated by the SD/MMC card connector.

P2.1

Signal

Name

Type Description

Alternate

Function

NFD7:0 I/O

Memory Data Bus

8-bit bidirectional data bus.

NFALE O

Address Latch Enable Signal

Asserted high during address write cycle.

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