Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 94)

AT85C51SND3Bx

7632A–MP3–03/06

ID Detection The ID pin transition is detected thanks to the following architecture:

Figure 58. ID Detection Input Block Diagram

By default, (no A-plug or B-plug), the macro is in the Peripheral mode (internal pull-up).

The IDTI interrupt is triggered when a A-plug (Host) is plugged or unplugged. The inter

rupt is not triggered when a B-plug (Peripheral) is plugged or unplugged.

The IDTI interrupt may be triggered even if the USB controller is disabled.

Registers

USB general registers

UID

USBSTA.1

Internal Pull Up

VDD

IDTI

USBINT.1

Table 102. USBCON Register

USBCON (1.E1h) – USB General Control Register

7 6 5 4 3 2 1 0

USBE HOST FRZCLK OTGPADE - - IDTE VBUSTE

Bit

Number

Bit

Mnemonic

Description

7 USBE

USB Controller Enable Bit

Set to enable the USB controller.

Clear to disable and reset the USB controller, to disable the USB transceiver and

to disable the USB controller clock inputs.

6 HOST

HOST Bit

Set to access to the Host registers.

Clear to access to the Device registers.

5 FRZCLK

Freeze USB Clock Bit

Set to disable the clock inputs (the “Resume Detection” is still active) and save

power consumption.

Clear to enable the clock inputs.

4 OTGPADE

OTG Pad Enable

Set to enable the OTG pad.

Clear to disable the OTG pad.

Note that this bit can be set/cleared even if USBE= 0 (this allows the VBUS

detection even if the USB macro is disable).

3-2 -

Reserved

The value read from these bits is always 0. Do not set these bits.

1 IDTE

ID Transition Interrupt Enable Bit

Set this bit to enable the ID Transition interrupt generation.

Clear this bit to disable the ID Transition interrupt generation.

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 262 263

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