Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 25)

AT85C51SND3Bx

7632A–MP3–03/06

Registers

Reset Value = 00011 0000b

Table 20. PCON Register

PCON (0.87h) – Power Control Register

7 6 5 4 3 2 1 0

VBCEN VBPEN DCPBST GF0 DCEN PMLCK PD IDL

Bit

Number

Bit

Mnemonic

Description

7 VBCEN

Battery Monitor Clock Enable Bit

Set to enable the clock of the battery monitoring.

Clear to disable the clock of the battery monitoring.

6 VBPEN

Battery Monitor Power Enable Bit

Set to power the battery monitoring.

Clear to unpower the battery monitoring.

5 DCPBST

DC-DC Converter Power Boost Bit

Set to disable DC-DC high power boost mode.

Clear to enable DC-DC high power boost mode.

4 GF0

General-purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

3 DCEN

DC-DC Converter Enable Bit

Set to start the DC-DC converter or maintain its activity while DCPWR pin is

asserted.

Clear to stop the DC-DC converter and shut off the device if not powered by an

external power supply.

2 PMLCK

Power Mode Lock Bit

Set to lock power-down or Idle mode entry by preventing PD or IDL bits from

being set by software.

Clear to unlock power-down or Idle mode entry.

1 PD

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode when PMLCK is cleared.

If IDL and PD are both set, PD takes precedence.

0 IDL

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode when PMLCK is cleared.

If IDL and PD are both set, PD takes precedence.

Table 21. PSTA Register

PSTA (0.86h) – Power Status Register

7 6 5 4 3 2 1 0

UVDET HVDET - - - WDTRST EXTRST PFDRST

Bit

Number

Bit

Mnemonic

Description

7 UVDET

USB Voltage Detect Flag

Set by hardware when 5V is detected on UVDD pin.

Cleared by hardware when 5V is not detected on UVDD pin.

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 262 263

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