Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 23)

AT85C51SND3Bx

7632A–MP3–03/06

Reset In order to secure the product functionality while in power-up or power-down phase or

while in running phase, a number of internal mechanisms have been implemented.

These mechanisms are listed below and detailed in the following paragraphs.

• External RST input

• Power Fail Detector (brown-out)

• Watchdog timer

• Pads control

Figure 12 details the internal reset circuitry.

Reset Source Reporting In order for the firmware to take specific actions depending on the source which has cur-

rently reset the device, activated reset source is reported to the CPU by EXTRST,

WDTRST, and PFDRST flags in PSTA register.

Figure 12. Internal Reset Circuitry

Pads Level Control As soon as one reset source is asserted, the pads go to their reset value. This ensures

that pads level is steady during reset (e.g.

NFWP set to low level and then protecting

Nand Flash against spurious writing).

The status of the Port pins during reset is detailed in Table 19.

Table 19. Pin State Under Reset Condition.

External RST Input In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a

low level has to be applied on the

RST pin. A bad level leads to a wrong initialization of

the internal registers like

SFRs, Program Counter… and to unpredictable behavior of

the microcontroller. A proper device reset initializes the AT85C51SND3B and vectors

the CPU to address 0000h.

RST input has a pull-up resistor allowing power-on reset by

simply connecting an external capacitor to V

as shown in Figure 13. A warm reset can

be applied either directly on the RST pin or indirectly by an internal reset source such as

the watchdog timer. Resistor value and input characteristics are discussed in the

Section “DC Characteristics”, page 241.

RST

To CPU Core

IOVDD

DCPWR

DC-DC

ON/OFF

VBAT

PFD

To Peripherals

To Pads Contro

WDT

SYSRST

OUT

EXTRST

PSTA.1

WDTRST

PSTA.2

PFDRST

PSTA.0

LVDD

RST

HVDD

1.8V

Reg

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 NFD7:0 NFWP NFCE0

Float H H H H H Float L H

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 262 263

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