Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 231)

231

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0001 0100b

4 MSTR

Master Mode Select

Set to select the master mode.

Clear to select the slave mode.

3 CPOL

SPI Clock Polarity Bit

Set to have the clock output set to high level in idle state.

Clear to have the clock output set to low level in idle state.

2 CPHA

SPI Clock Phase Bit

Set to have the data sampled when the clock returns to idle state (see CPOL).

Clear to have the data sampled when the clock leaves the idle state (see CPOL).

1-0 SPR1:0

SPI Rate Bits 0 and 1

Refer to Ta bl e 250 for bit rate description.

Table 252. SPSCR Register

SPSCR (1.92h) – SPI Status and Control Register

7 6 5 4 3 2 1 0

SPIF - OVR MODF SPTE UARTM SPTEIE MODFIE

Bit

Number

Bit

Mnemonic

Description

7 SPIF

SPI Interrupt Flag

Set by hardware when an 8-bit shift is completed.

Cleared by hardware to indicate data transfer is in progress or has been

acknowledged by a clearing sequence: reading or writing SPDAT after reading

SPSCR.

6 -

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5 OVR

Overrun Error Flag

Set by hardware when a byte is received whereas SPIF is set (the previous

received data is not overwritten).

Cleared by hardware when reading SPSCR.

4 MODF

Mode Fault Interrupt Flag

Set by hardware to indicate that the SS pin is in inappropriate logic level.

Cleared by hardware when reading SPSCR

When MODF error occurred:

- In slave mode: SPI interface ignores all transmitted data while SS remains high.

A new transmission is perform as soon as SS returns low.

- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN

bit in SPCON register).

3 SPTE

Serial Peripheral Transmit register Empty Interrupt Flag

Set by hardware when transmit register is empty (if needed, SPDAT can be

loaded with another data).

Cleared by hardware when transmit register is full (no more data should be

loaded in SPDAT).

2 UARTM

Serial Peripheral UART mode

Set to select UART mode: data is transmitted LSB first.

Clear to select SPI mode: data is transmitted MSB first.

Bit

Number

Bit

Mnemonic Description

1 2 ... 226 227 228 229 230 231 232 233 234 235 236 ... 262 263

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