Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 112)

112

AT85C51SND3Bx

7632A–MP3–03/06

Table 111. Abort flow

Isochronous Mode For Isochronous IN endpoints, it is possible to automatically switch the banks on each

start of frame (SOF). This is done by setting ISOSW. The CPU has to fill the bank of the

endpoint; the bank switching will be automatic as soon as a SOF is seen by the

hardware.

A clear of FIFOCON does not have any effects in this mode.

In the case that a SOF is missing (noise on USB pad, …), the controller will automati-

cally build internally a “pseudo” start of frame and the bank switching is made. The SOFI

interrupt is triggered and the frame number FNUM10:0 is increased.

Underflow An underflow can occur during IN stage if the host attempts to read a bank which is

empty. In this situation, the UNDERFI interrupt is triggered.

An underflow can also occur during OUT stage if the host send a packet while the banks

are already full. Typically, he CPU is not fast enough. The packet is lost.

It is not possible to have underflow error during OUT stage, in the CPU side, since the

CPU should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)

CRC Error A CRC error can occur during OUT stage if the USB controller detects a bad received

packet. In this situation, the STALLI interrupt is triggered. This does not prevent the

RXOUTI interrupt from being triggered.

Overflow In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT

stage, if the host attempts to write in a bank that is too small for the packet. In this situa

tion, the OVERFI interrupt is triggered (if enabled). The packet is acknowledged and the

RXOUTI interrupt is also triggered (if enabled). The bank is filled with the first bytes of

the packet.

It is not possible to have overflow error during IN stage, in the CPU side, since the CPU

should write only if the bank is ready to access data (TXINI=1 or RWAL=1).

Endpoint

Abort

Abort done

Abort is based on the fact

that no banks are busy,

meaning that nothing has to

be sent.

Disable the TXINI interrupt.

Endpoint

reset

NBUSYBK

Yes

Clear

UEIENX.

TXINE

KILLBK=1

Yes

Kill the last written

bank.

Wait for the end of the

procedure.

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