Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 78)

AT85C51SND3Bx

7632A–MP3–03/06

Data Flow Controller The Data Flow Controller (DFC) embedded in the AT85C51SND3Bx is the multimedia

data transfer manager. Up to two data transfers can be established through two physical

data channels between a source peripheral and a destination peripheral.

Figure 45

shows which peripherals are connected to the internal bus which are: the CPU internal

bus, the multimedia data bus and the DFC control bus.

Figure 45. DFC Internal Architecture

CPU Interface The DFC interfaces to the C51 core through the following special function registers:

DFCON the DFC control register, DFCSTA the channel status register, DFCCON the

channel control register, DFD0 and DFD1, the physical channel 0 and channel 1 data

flow descriptor registers and DFCRC the CRC data register.

Clock Unit The DFC clock is generated based on the clock generator as detailed in

Section “DFC/NFC Clock Generator”, page 30. Depending on the power mode (USB

powered or battery powered) and the throughput desired, different clock values may be

selected to control the data transfer. The DFC does not receive its system clock until

DFEN bit in DFCON is set, i.e. DFC enabled.

Data Flow Descriptor As shown in Table 91 the data flow is characterized by a 5-byte data flow descriptor: the

DFD composed of 4 fields. The data flow descriptor is written byte by byte to DFD0

(channel 0) or to DFD1 (channel 1). As soon as a DFD has been fully written, the chan

nel is enabled and data flow transfer starts when both source and destination are ready

to send and receive data respectively.

RAM

USB

AUP

SPI

SIO

NFC

MMC

CPU

Internal Bus

DFC

Control Bus

Multimedia

Data Bus

DFC

CLOCK

DFEN

DFCON.0

PSI

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 262 263

Keine Kommentare

Atmel AT85DVK-07 Spezifikationen Seite 78