Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 216)

216

AT85C51SND3Bx

7632A–MP3–03/06

Figure 109. Baud Rate Generator Block Diagram

Table 240. Baud Rate Generator Value (12x oversampling)

Note: 1. This high frequency available through the clock generator requires PLL usage. It is

recommended to use it only for high baud rate that can not be achieved using oscilla-

tor frequency.

Baud

Rate

SIO

= 12 MHz F

SIO

= 16 MHz F

SIO

= 20 MHz F

SIO

= 24 MHz F

SIO

= 120 MHz

(1)

A B C ε % A B C ε % A B C ε % A B C ε % A B C ε %

9600 125 6 5 0 110 99 125 0 124 5 7 0.007 125 3 5 0 110 15 142 0.033

19200 125 12 5 0 125 9 5 0 124 10 7 0.007 125 6 5 0 110 49 232 0.004

38400 125 24 5 0 125 18 5 0 124 20 7 0.007 125 12 5 0 110 49 116 0.004

57600 125 36 5 0 125 27 5 0 124 30 7 0.007 125 18 5 0 124 5 7 0.007

115200 125 72 5 0 125 54 5 0 124 60 7 0.007 125 36 5 0 124 10 7 0.007

230400 115 53 2 0.016 125 108 5 0 120 83 5 0.067 125 72 5 0 217 5 1 0.007

460800 115 53 1 0.016 120 83 2 0.067 112 31 1 0.111 115 53 2 0.016 217 10 1 0.007

921600 115 106 1 0.016 120 83 1 0.067 112 62 1 0.111 115 53 1 0.016 118 87 8 0.002

1M 1 1 1 0 112 84 1 0 115 69 1 0 110 55 1 0 120 12 1 0

1.5M - - - - - - - - 110 99 1 0 112 84 1 0 120 18 1 0

2M - - - - - - - - - - - - 1 1 1 0 115 23 1 0

4M - - - - - - - - - - - - - - - - 115 46 1 0

8M - - - - - - - - - - - - - - - - 115 92 1 0

ADIV7:0

SBRG1

BDIV7:0

SBRG2

Fractional

Post-Divider

A ÷ B

CDIV7:0

SBRG0

To serial

Receiver &

Integer

Pre-Divider

÷ C

SIO

CLOCK

SBRG

CLOCK

Transmitter

1 2 ... 211 212 213 214 215 216 217 218 219 220 221 ... 262 263

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