Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 225)

225

AT85C51SND3Bx

7632A–MP3–03/06

The transmission begins by writing to SPDAT through CPU or DFC. Writing to SPDAT

writes to an intermediate register which is automatically loaded to the shift register if no

transmission is in progress. Reading SPDAT through CPU or DFC reads an intermedi

ate register updated at the end of each transfer.

The byte begins shifting out on the MOSI pin under the control of the bit rate generator.

This generator also controls the shift register of the slave peripheral through the SCK

output pin. As the byte shifts out, another byte shifts in from the slave peripheral on the

MISO pin. The byte is transmitted most significant bit (MSB) first when UARTM bit in

SPCR is cleared or least significant bit (LSB) first when UARTM bit in SPCR is set. The

end of transfer is signaled by SPIF being set.

In case SPI is the source of a DFC channel (slave device data read), SPDAT is first

loaded with a dummy byte (

FFh value) to initiate the transfer. Then transfer continues by

transmitting the shift register content which is the last data received.

When the AT85C51SND3Bx is the only master on the bus, it can be useful not to use

SS pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in

SPCON.

Figure 117. SPI Master Mode Block Diagram

Note: MSTR bit in SPCON is set to select master mode.

Slave Mode The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has

been loaded in SPDAT.

Note: The SPI Module should be configured as a slave before it is enabled (SPEN set).

Figure 118 shows the SPI block diagram in slave mode. In slave mode, before a data

transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must

remain low until the transmission of the byte is complete. In the slave SPI module, data

enters the shift register through the MOSI pin under the control of the serial clock pro

vided by the master SPI module on the SCK input pin. When the master starts a

transmission, the data in the shift register begins shifting out on the MISO pin. The end

of transfer is signaled by SPIF being set.

UARTM

SPSCR.2

SPR2:0

SPCON

PER

CLOCK

SPEN

SPCON.6

8-bit Shift Register

Bit Rate

MOSI/P3.1

MISO/P3.0

SCK/P3.2

CPOL

SPCON.3

CPHA

SPCON.2

CPU or DFC Bus

SPDAT RD

Control

MODF

SPSCR.4

SS/P3.3

SSDIS

SPCON.5

OVR

SPSCR.6

SPIF

SPSCR.7

Generator

and

Clock Logic

SPDAT WR

SPTE

SPSCR.3

1 2 ... 220 221 222 223 224 225 226 227 228 229 230 ... 262 263

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