
117
AT85C51SND3Bx
7632A–MP3–03/06
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Reset Value = 0000 0000b
0 SUSPE
Suspend Interrupt Enable Bit
Set to enable the SUSPI interrupt.
Clear to disable the SUSPI interrupt.
Table 115. UDADDR Register
UDADDR (1.DBh) – USB Device Address Register
7 6 5 4 3 2 1 0
ADDEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
Bit
Number
Bit
Mnemonic
Description
7 ADDEN
Address Enable Bit
Set to activate the UADD (USB address).
Cleared by hardware. Clearing by software has no effect.
See Section “Address Setup” for more details.
6-0 UADD6:0
USB Address Bits
Set to configure the device address.
Shall not be cleared.
Table 116. UDFNUMH Register
UDFNUMH (1.DCh) – USB Device Frame Number High Register
7 6 5 4 3 2 1 0
- - - - - FNUM10 FNUM9 FNUM8
Bit
Number
Bit
Mnemonic
Description
7-3 -
Reserved
The value read from these bits is always 0. Do not set these bits.
2-0 FNUM10:8
Frame Number Upper Flag
Set by hardware. These bits are the 3 MSB of the 11-bits Frame Number
information. They are provided in the last received SOF packet. FNUM is
updated if a corrupted SOF is received.
Table 117. UDFNUML Register
UDFNUML (1.DDh) – USB Device Frame Number Low Register
7 6 5 4 3 2 1 0
FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0
Bit
Number
Bit
Mnemonic Description
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