Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 157)

157

AT85C51SND3Bx

7632A–MP3–03/06

Figure 75. Audio DAC Interface Block Diagram

Clock Controller As soon as audio DAC interface is enabled by setting ADIEN bit in ADICON0, the mas-

ter clock generated by the clock generator (see Section “Clock Generator”) is output on

the OCLK pin which is the DAC over-sampling clock. The over-sampling ratio is defined

by OVERS1:0 bits in ADICON0 according to

Table 164 and is selected depending on

the DAC capabilities.

Table 164. Audio DAC Interface Over-sampling Ratio

For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or

32 bits per channel using the DSIZE bit in ADICON0 (see

Section "Data Converter",

page 157), and the word selection signal (DSEL) is programmable for outputting left

channel on low or high level according to CSPOL bit in ADICON0 as shown in

Figure 76.

Figure 76. DSEL Output Polarity

Data Converter The data converter block converts the audio stream coming from the audio processor to

a serial format. For accepting all PCM formats and I

S format, JUST4:0 bits in ADICON1

Figure 77, these bits allow

MSB justification by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 =

10000, I

S Justification by setting JUST4:0 = 00001, and more than 16-bit LSB justifica-

tion by filling the low significant bits with logic 0.

CSPOL

ADICON0.4

AUD

CLOCK

DSIZE

ADICON0.3

DSEL

Clock Controller

DCLK

DDAT

OCLK

JUST4:0

ADICON1.4:0

ADIEN

ADICON0.0

OVERS1:0

ADICON0.2:1

Data

Audio Data From

Audio Processor

Converter

OVERS1:0 Over-sampling Ratio

00 Reserved

01 128 · F

10 256 · F

11 384 · F

Left Channel Right Channel

CSPOL = 1

CSPOL = 0

Left Channel Right Channel

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