Atmel AT85DVK-07 Spezifikationen PDF herunterladen (Seite 125)

125

AT85C51SND3Bx

7632A–MP3–03/06

Reset Value = 0000 0000b

Table 128. UEDATX Register

UEDATX (1.D3h) – USB Endpoint Data Register

7 6 5 4 3 2 1 0

DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0

Bit

Number

Bit

Mnemonic

Description

7-0 DAT7:0

Data Bits

Set by the software to read/write a byte from/to the endpoint FIFO selected by

EPNUM.

Table 129. UEBCHX Register

UEBCHX (1.D4h) – USB Endpoint Byte Counter High Register

7 6 5 4 3 2 1 0

- - - - - BYCT10 BYCT9 BYCT8

Bit

Number

Bit

Mnemonic

Description

7-3 -

Reserved

The value read from these bits is always 0. Do not set these bits.

2-0 BYCT10:8

Byte count (high) Bits

Set by hardware. This field is the MSB of the byte count of the FIFO endpoint.

The LSB part is provided by the UEBCLX register.

Table 130. UEBCLX Register

UEBCLX (1.D5h) – USB Endpoint Byte Counter Low Register

7 6 5 4 3 2 1 0

BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0

Bit

Number

Bit

Mnemonic

Description

7-0 BYCT7:0

Byte Count (low) Bits

Set by the hardware. BYCT10:0 is:

- (for IN endpoint) increased after each writing into the endpoint and

decremented after each byte sent,

- (for OUT endpoint) increased after each byte sent by the host, and

decremented after each byte read by the software.

1 2 ... 120 121 122 123 124 125 126 127 128 129 130 ... 262 263

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