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Common Features Description

Atmel 8051 Microcontrollers Hardware Manual 2-76

4316E–8051–01/07

2.5.3 Port Loading and

Interfacing

The output buffer of Ports 1, 2 and 3 can each drive 3LS TTL inputs. The pins can be

driven by open-collector and open-drain outputs, but note that 0-to-1 transition will not

be fast. In the CMOS device, an input 0 turns off pull-up P3, leaving only the weak pull-

up P2 to drive the transistor. Figure 2-6 shows an example where the port is driven by

an open drain transistor t

. The parasitic capacitance is equal to 1000pF.

Figure 2-6. Port Interfacing

The above diagram show the behavior of the port during 0 to 1 transition.

In the area A only pull-up P2 sinks the capacitor and takes 5 µs to switch from 0 volt to 2

volts. In the area B, pull-up P2 and P3 feed the capacitor and the time to charge the capacitor is

divide roughly by ten. So this figure shows it takes some machine cycles before having a true

high level during a 0-to-1 transition.

Figure 2-7. Port Behavior During 0-to-1 Transition

2.5.4 Read-Modify-Write

Feature

Some instructions that read a port read the latch and others read the pin. Which instruc-

tions perform what functions? The instructions that read the latch rather than the pin are

the ones that read a value, possibly change it, and then rewrite it to the latch. These are

called “read-modify-write” instructions. The instructions listed below are read-modify-

write instructions. When the destination operand is a port, or a port bit, these instruc-

tions read the latch rather than the pin:

ANL (logical AND, e.G., ANL P1,A)

ORL (logical OR, e.g., ORL P2,A)

XRL (logical EX-OR, e.g., XRL P3,A)

JBC (jump if bit = 1 and clear bit, e.g., JBC P1.1, LABEL)

CPL (complement bit, e.g., CPL P3.0)

INC (increment, e.g., INC P2)

DEC (decrement, e.g., DEC P2)

Voltage (V)

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Atmel C51 Handbuch Seite 76