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AT89C51RB2/RC2

4180E–8051–10/06

Table 16. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

Reset Value = XXXX XXX0b

Not bit addressable

76543210

-------SPIX2

Bit

Number

Bit

Mnemonic Description

7-Reserved

6-Reserved

5-Reserved

4-Reserved

3-Reserved

2-Reserved

1-Reserved

0SPIX2

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 126 127

Features 1
Description 1
AT89C51RB2/RC2 10
Table of Contents 124
Regional Headquarters 127

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