
Software Implementation
ATEVK525 Mass Storage Board for AVR 3-17
7740B–AVR–03/08
3.2 Performances
3.2.1 Benchmark
Table 3-1 . Memory speed benchmark (8MHz clocked microcontroller
(1)
)
Note: 1. The AVR micro controller cannot be clocked at 16MHz since this configuration
requires a 4.5V minimum power supply whereas NAND Flash or SD/MMC devices do
not withstand such a voltage level on I/Os. However, DataFlash are 5V-tolerant, and
speed measurements have been done independently of this evaluation board: for
45DB321, write speed is 40KB/sec and read speed is 300KB/sec. For 45DB642,
write speed is 80KB/sec and read speed is 300KB/sec.
2. In the K9K2G08UOM device, the COPYBACK instruction cannot be used in all the
memory plane, since it is efficient only between size-limited zones. This problem con-
cern several other memorie devices.
3.2.2 Direct limitations
The limitations on reading operations are:
– Dataflash: SPI bus frequency, internal read access speed
– SD/MMC: SPI bus frequency, internal read access speed
– NAND Flash: USB maximum data rate
The limitations on writing operations are:
– Dataflash: internal write access speed, page write duration & size, SPI bus
frequency
– SD/MMC: internal write access speed and duration, SPI bus frequency
– NAND Flash: memory internal writing structure (COPYBACK support or not,
page write and block erase duration, page size), USB maximum data rate
Memory
Speed (KBytes/sec)
Read Write
DataFlash AT45DB321 (page 512B) 200 35
AT45DB642 (page 1024B) 200 55
MMC/SD SD 1GB 80x 235 235
SD 256MB 215 155
MMC Plus 2GB Premium 235 170
MMC 32MB (old revision) 215 50
NAND Flash M29F2G008AAC (page 2KB, copyback) 1095 860
K9K2G08UOM (page 2KB, copyback disabled
(2)
) 1005 660
HYF31DS512805 (page 512B, no copyback) 1110 590
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