Atmel C51 Datenblatt PDF herunterladen (Seite 19)

AT89S53

4-233

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 11. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven, as shown in Figure 12.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invokes idle mode should not write to a port pin or to exter-

nal memory.

Power Down Mode

In the power down mode, the oscillator is stopped and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. Exit from power down can be initiated either by a

hardware reset or by an enabled external interrupt. Reset

redefines the SFRs but does not change the on-chip RAM.

The reset should not be activated before V

is restored to

its normal operating level and must be held active long

enough to allow the oscillator to restart and stabilize.

To exit power down via an interrupt, the external interrupt

must be enabled as level sensitive before entering power

down. The interrupt service routine starts at 16 ms (nomi-

nal) after the enabled interrupt pin is activated.

Figure 11.

Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 12.

External Clock Drive Configuration

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power Down Internal 0 0 Data Data Data Data

Power Down External 0 0 Float Data Data Data

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 33 34

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