Atmel C51 Datenblatt

Atmel 8051 Microcontroller Family - Product Selection GuideMax speed depends on Vcc voltage. Frequencies and Currents listed are forVcc= 5.0V & T=

AT89S534-224Table 4. SPCR—SPI Control RegisterSPCR Address = D5H Reset Value = 0000 01XXBSPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0Bit76543210Symbol Funct

AT89S534-225Data Memory - RAMThe AT89S53 implements 256 bytes of RAM. The upper128 bytes of RAM occupy a parallel space to the SpecialFunction Registe

AT89S534-226Timer 0 and 1Timer 0 and Timer 1 in the AT89S53 operate the same wayas Timer 0 and Timer 1 in the AT89C51, AT89C52 andAT89C55. For further

AT89S534-227EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to0FFFFH and then sets the TF2 bit upon overflow. The over-flow also causes the timer regi

AT89S534-228Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)Figure 4. Timer 2 in Baud Rate Generator ModeOSCSMOD1RCLKTCLKRxCLOCKTxCLOCKT2EX PINT2 PINTR

AT89S534-229Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that the baudrates f

AT89S534-230Programmable Clock OutA 50% duty cycle clock can be programmed to come out onP1.0, as shown in Figure 5. This pin, besides being a regu-la

AT89S534-231clock output in the master mode but is the clock input in theslave mode. Writing to the SPI data register of the masterCPU starts the SPI

AT89S534-232InterruptsThe AT89S53 has a total of six interrupt vectors: two exter-nal interrupts (INT0 and INT1), three timer interrupts (Tim-ers 0, 1

AT89S534-233Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use

Atmel 8051 Microcontroller Family - Product Selection GuideFor further information please contact Equinox Technologies UK Ltd on Tel: +44 (0) 1204 529

AT89S534-234Program Memory Lock BitsThe AT89S53 has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain the addi-tio

AT89S534-2358. Repeat steps 3 through 7 changing the address anddata for the entire 12K-byte array or until the end of theobject file is reached.9. Po

AT89S534-236Instruction SetNotes: 1. DATA polling is used to indicate the end of a write cycle which typically takes less than 2.5 ms at 5V.2. “x” = d

AT89S534-237Flash Parallel Programming ModesNotes: 1. “h” = weakly pulled “High” internally.2. Chip Erase and Serial Programming Fuse require a 10-ms

AT89S534-238Figure 13. Programming the Flash MemoryP1P2.6P3.6P2.0 - P2.5A0-A7ADDR.0000H/2FFFHSEE FLASHPROGRAMMINGMODES TABLE3-24 MhzA8 - A13P0+5VP2.7P

AT89S534-239Flash Programming and Verification Characteristics - Parallel ModeTA = 0°C to 70°C, VCC = 5.0V ± 10%Symbol Parameter Min Max UnitsVPPProgr

AT89S534-240Flash Programming and Verification Waveforms - Parallel ModeSerial Downloading WaveformsSERIAL CLOCK INPUTSERIAL DATA INPUTSCK/P1.7MOSI/P1

AT89S534-241Absolute Maximum Ratings*Operating Temperature... -55°C to +125°C*NOTICE: Stresses beyond those listed unde

AT89S534-242AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all otherout

AT89S534-243External Program Memory Read CycleExternal Data Memory Read Cycle

4-217Features•Compatible with MCS-51™ Products•12K Bytes of In-System Reprogrammable Downloadable Flash Memory– SPI Serial Interface for Program Downl

AT89S534-244External Data Memory Write CycleExternal Clock Drive WaveformsExternal Clock DriveSymbol Parameter VCC = 4.0V to 6.0VMin Max Units1/tCLCLO

AT89S534-245Serial Port Timing: Shift Register Mode Test ConditionsThe values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 p

AT89S534-246Notes: 1. XTAL1 tied to GND for ICC (power down)2. Lock bits programmed

AT89S534-247Ordering InformationSpeed(MHz)PowerSupplyOrdering Code Package Operation Range16 4.0V to 6.0V AT89S53-16AAAT89S53-16JAAT89S53-16PA44A44J40

AT89S534-248

AT89S534-218Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink

AT89S534-219Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7FLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDPTRINSTRUCTION

AT89S534-220Pin DescriptionFurthermore, P1.4, P1.5, P1.6, and P1.7 can be configuredas the SPI slave port select, data input/output and shiftclock inp

AT89S534-221XTAL1Input to the inverting oscillator amplifier and input to theinternal clock operating circuit. XTAL2Output from the inverting oscillat

AT89S534-222User software should not write 1s to these unlisted loca-tions, since they may be used in future products to invokenew features. In that c

AT89S534-223Dual Data Pointer Registers To facilitate accessing exter-nal data memory, two banks of 16 bit Data Pointer Regis-ters are provided: DP0 a